1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to field effect transistors and manufacturing techniques on the basis of stressed dielectric layers formed above the transistors used for generating a strain in channel regions of the transistors.
2. Description of the Related Art
Integrated circuits are typically comprised of a large number of circuit elements located on a given chip area according to a specified circuit layout, wherein, in complex circuits, the field effect transistor represents one predominant circuit element. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry based on field effect transistors, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, may be a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One issue associated with reduced gate lengths is the occurrence of so-called short channel effects, which may result in a reduced controllability of the channel conductivity. Short channel effects may be countered by certain design techniques, some of which, however, may be accompanied by a reduction of the channel conductivity, thereby partially offsetting the advantages obtained by the reduction of critical dimensions.
In view of this situation, it has been proposed to enhance device performance of the transistor elements not only by reducing the transistor dimensions but also by increasing the charge carrier mobility in the channel region for a given channel length, thereby increasing the drive current capability and thus transistor performance. For example, the lattice structure in the channel region may be modified, for instance, by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons, which in turn may directly translate into a corresponding increase of the conductivity of N-type transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
One efficient approach in this respect is a technique that enables the creation of desired stress conditions within the channel region of different transistor elements by adjusting the stress characteristics of a dielectric layer stack that is formed above the basic transistor structure. The dielectric layer stack typically comprises one or more dielectric layers which may be located close to the transistor and which may also be used in controlling a respective etch process in order to form contact openings to the gate and drain and source terminals. Therefore, an effective control of mechanical stress in the channel regions, i.e., effective stress engineering, may be accomplished by individually adjusting the internal stress of these layers, which may also be referred to as contact etch stop layers, and by positioning a contact etch stop layer having an internal compressive stress above a P-channel transistor or positioning a contact etch stop layer having an internal tensile strain above an N-channel transistor, thereby creating compressive and tensile strain, respectively, in the respective channel regions.
Typically, the contact etch stop layer is formed by plasma enhanced chemical vapor deposition (PECVD) processes above the transistor, i.e., above the gate structure and the drain and source regions, wherein, for instance, silicon nitride may be used due to its high etch selectivity with respect to silicon dioxide, which is a well-established interlayer dielectric material. Furthermore, PECVD silicon nitride may be deposited with a high intrinsic stress, for example, up to 2 Giga Pascal (GPa) or significantly higher of compressive stress and up to 1 GPa and significantly higher of tensile stress, wherein the type and the magnitude of the intrinsic stress may be efficiently adjusted by selecting appropriate deposition parameters. For example, ion bombardment, deposition pressure, substrate temperature, gas flow rates and the like represent respective parameters that may be used for obtaining the desired intrinsic stress.
The deposition parameters used for forming one or both types of highly stressed dielectric layers may also have an influence on the deposition behavior, for instance with respect to the gap filling capabilities of the PECVD process. For example, when forming stressed dielectric layers comprising a high compressive or tensile stress level above transistor elements formed on the basis of design rules requiring a gate length of 50 nm and less, the limited conformal deposition capabilities of the deposition process may result in less pronounced overall device performance, in particular when semiconductor devices are considered that include densely packed device areas, such as memory areas of complex central processing units (CPUs). That is, in many semiconductor devices, a respective balance between design-related performance characteristics, such as the overall transistor architecture, the transistor width and the like, may be implemented, wherein efficient strain-inducing mechanisms may also play an important role. For example, as previously explained, in particular, relatively high compressive stress levels may be created in a silicon nitride material, thereby offering the potential for significantly enhancing performance of P-channel transistors for a standard crystallographic configuration of the silicon layer. Since typically the overall charge carrier mobility of P-channel transistors may be less compared to the charge carrier mobility of N-channel transistors, the respective imbalance in drive current capability may be taken into consideration by other design measures, such as adapting transistor width of P-channel transistors and the like. By providing a highly stressed dielectric material, however, respective design measures may be required to a significantly lesser degree, thereby enhancing overall design flexibility and providing the potential for further increasing the overall packing density of the semiconductor device. In order to create a highly efficient strain-inducing mechanism, the highly stressed dielectric material may be formed above the transistors, substantially without requiring additional process steps, as may typically be required for sophisticated dual stress liner approaches in which stressed dielectric materials of different internal stress types may be positioned individually above respective transistor types. Consequently, this process technology may be an attractive approach for substantially enhancing the overall device performance without the additional process complexity. However, it turns out that a corresponding gain in overall device performance may be less pronounced as expected, as will be described in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, above which is formed a semiconductor layer 102. The substrate 101 may represent any appropriate carrier material for forming thereabove the semiconductor layer 102, which is typically a silicon layer, which may include other components such as germanium, carbon and the like. The semiconductor layer 102 may represent an upper portion of the substrate 101 thereby providing a bulk configuration, while, in other cases, a buried insulating layer (not shown) may be located between the substrate 101 and the semiconductor layer 102, thereby defining a silicon-on-insulator (SOI) configuration.
The semiconductor device 100 further comprises one or more first transistors 150A, which are assumed to be P-channel transistors, the performance of which is to be enhanced by providing a highly stressed dielectric material, as discussed above. Furthermore, one or more second transistors 150B may be formed in and above the semiconductor layer 102, wherein, in the example shown, the one or more second transistors 150B may represent transistors in which compressive stress may negatively affect the overall performance, while a moderately densely packed device geometry may also be realized by the transistors 150B. That is, a distance between neighboring transistor elements 150B may be comparable to the transistor dimensions in the transistor length direction, which is represented by the horizontal direction in FIG. 1a. For example, the plurality of second transistors 150B may be provided in a memory area of the semiconductor device 100.
The transistors 150A, 150B typically comprise a gate electrode structure 153, which may comprise gate electrode material 153A, possibly in combination with a metal silicide region 153C, if the gate electrode material 153A may initially be comprised of polysilicon. Furthermore, the gate electrode structure 153 comprises a gate insulation layer 153B, which separates the gate electrode material 153A from a channel region 152, which is defined in the semiconductor layer 102. The channel region 152 is laterally enclosed by drain and source regions 151 having an appropriate dopant profile in the lateral and vertical direction, as required by the overall transistor configuration. It should be appreciated that, although the transistors 150A, 150B are illustrated so as to have basically the same configuration, these transistors may differ from each other, for instance, with respect to the thickness and/or composition of the gate insulation layers 153B, the gate length, i.e., in FIG. 1a the horizontal extension of the gate electrode material 153A, the conductivity type and thus the dopant species used for defining the drain and source regions 151, the respective vertical and lateral distribution of the dopant species in the drain and source regions 151 and the like.
Furthermore, as shown, a sidewall spacer structure 154 may be provided at sidewalls of the gate electrode structure 153. Moreover, the conductivity of the drain and source regions 151 may be increased by providing a metal silicide region 151A therein. Moreover, a compressively stressed contact etch stop layer 110 is formed above the first and second transistors 150A, 150B with an appropriate thickness so as to provide a desired high strain level in the channel region 152 of the transistor 150A and also comply with the deposition capabilities of the respective PECVD technique in order to not unduly create deposition-related non-uniformities at and above the transistors 150B, in particular in densely packed device regions, as shown. The stressed contact etch stop layer 110 may be comprised of silicon nitride and the like.
The semiconductor device 100 as shown in FIG. 1a may be formed on the basis of well-established process techniques in which the transistors 150A, 150B may be formed by providing appropriate materials for the gate insulation layer 153B and the gate electrode 153A. For this purpose, oxidation and/or deposition recipes may be used for the gate dielectric material followed by the deposition of an appropriate gate electrode material, such as polysilicon. Thereafter, sophisticated patterning strategies may be used to obtain the gate electrode structure 153 with a desired gate length. Thereafter, the drain and source regions 151 may be defined on the basis of complex implantation sequences, or, additionally, the spacer structure 154 may act as an implantation mask wherein the overall width of the spacer structure 154 may be modified during the respective implantation sequence so as to obtain the desired lateral shielding effect. Next, the metal silicide regions 151A, 153C may be formed, for instance, in a common manufacturing sequence, followed by the deposition of the contact etch stop layer 110 on the basis of appropriately selected deposition parameters in order to obtain the desired high internal stress level, which is assumed to be a compressive stress level for enhancing performance of the P-channel transistor 150A. For sophisticated devices, a thickness of the contact etch stop layer 110 may be in the range of approximately 120-150 nm in order to avoid deposition-related irregularities at the transistors 150B. That is, typically, the thickness of the layer 110 is a compromise between a substantially void-free deposition above the densely packed device region as represented by the second transistors 150B and the requirement for a high strain in the channel region 152 of the transistor 150A, which may involve the deposition of a high amount of stressed dielectric material and thus of a moderately great thickness of the layer 110.
As previously discussed, the required performance of the transistors 150B may be obtained by design-specific criteria, while the strain-inducing mechanism provided by the layer 110 for the first transistor 150A may be required so as to provide the specified overall performance of the device 100. In the embodiment shown, the dielectric layer 110 may be directly deposited on the metal silicide regions 151A, thereby providing a highly efficient strain-inducing mechanism wherein, however, a respective compressive strain may also be created in the transistors 150B, thereby reducing the performance thereof. Consequently, a respective stress relaxation is performed for the second transistors 150B on the basis of an ion implantation process.
FIG. 1b schematically illustrates the semiconductor device 100 during a respective ion implantation process 104, which may be performed on the basis of an implantation mask 105 that covers the first transistor 150A while exposing the second transistors 150B. During the ion implantation process 104, an appropriate species, such as germanium, silicon and the like, may be used for bombarding the exposed portion of the layer 110, thereby modifying the molecular structure and hence relaxing the internal stress level. However, in particular in densely packed device regions as shown, the local thickness of the layer 110 may vary significantly so that, for a specified implantation energy and dose, respective varying degrees of relaxation may be created, which may finally result in substantially relaxed portions 110A, typically in the upper portion of the layer 110, and in substantially non-relaxed portions 110B, which may thus exert a significant stress on the transistors 150B, thereby creating non-desired compressive strain in the channel regions 152. However, a respective adaptation of the ion implantation parameters may be difficult to be achieved since an increase of implantation energy, possibly in combination with an increased dose, may finally result in a significant modification of respective transistor areas, such as the metal silicide regions 153C, 151A, and gate electrode 153A and the like.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.